By Charles E. Stroud
A contemporary technological enhance is the paintings of designing circuits to check themselves, often called a integrated Self-Test (BIST). this concept was once first proposed round 1980 and has grown to turn into some of the most very important checking out options on the present time, in addition to for the long run. This ebook is written from a designer's viewpoint and describes the most important BIST methods which have been proposed and carried out because 1980, besides their merits and barriers. The BIST techniques contain the integrated common sense Block Observer, pseudo-exhaustive BIST concepts, round BIST, scan-based BIST, BIST for normal buildings, BIST for FPGAs and CPLDs, mixed-signal BIST, and the combination of BIST with concurrent fault detection suggestions for online trying out. specific consciousness is paid to system-level use of BIST so one can maximize the advantages of BIST via diminished trying out time and value in addition to excessive diagnostic answer. the writer spent 15 years as a dressmaker at Bell Labs the place he designed over 20 creation VLSI units and three creation circuit forums. 16 of the VLSI units contained BIST of varied forms for normal constructions and normal sequential common sense, together with the 1st BIST for Random entry stories (RAMs), the 1st thoroughly self-testing built-in circuit, and the 1st BIST for mixed-signal structures at Bell Labs. He has spent the prior 10 years in academia the place his learn and improvement maintains to target BIST, together with the 1st BIST for FPGAs and CPLDs in addition to persevered paintings within the region of BIST for basic sequential common sense and mixed-signal platforms. He holds 10 US patents (with five extra pending) for varied forms of BIST methods. hence, the writer brings a distinct combination of data and adventure to this sensible advisor for designers, try out engineers, product engineers, process diagnosticians, and managers.
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Extra resources for A Designer’s Guide to Built-In Self-Test
As a result, the bridging faults with the higher probability of occurrence have a bigger impact on the weighted fault coverage. 9943% . Therefore, there was no need to continue with test development for higher fault coverage since the faults that were not detected were those faults that were the least likely to occur. 5% unweighted bridging fault coverage. 9% indicating that the bridging faults being detected by this set of tests were those that were the least likely to occur. This case contradicts the notion that high stuck-at gate-level fault coverage implies high bridging fault coverage.
2. Fault Models and Detection The same minimum set of test vectors needed to detect the transistor-level stuck-on faults will also detect the gate-level stuck-at faults. 4d. These are also the same test vectors that detect the transistor stuck-off faults. However, the ordering of the test vectors is critical in the case of the stuck-off fault detection, Also critical is the interleaving of the all 0s test pattern for setting up the necessary logic 1 value at the output of the NOR gate. Therefore, for a K-input static CMOS elementary logic gate (NAND or NOR), a minimum of 2K vectors are required to detect all of the transistor-level faults.
For any K-input elementary logic gate (AND, NAND, OR, NOR and Inverter), only K+1 vectors are needed to detect 100% of the single stuck-at gate-level faults. For an AND or NAND gate, the minimum set of test vectors includes the all 1s pattern and the set of patterns that include a single logic 0 in a field of 1s. For an OR or NOR gate, the minimum set of test vectors includes the all 0s pattern and the set of patterns that include a single logic 1 in a field of 0s. Note that the exclusive-OR gate is not considered to be an elementary logic gate since it is generally constructed from multiple gates such that the set of faults depend on its construction, yet all four test patterns are needed for complete testing regardless of its construction.